The present invention relates to the field of electronic circuit devices (such as computer system components) cooled by a cooling fluid conduit network (i.e., a fluid-cooling pipeline), which otherwise consumes a clock signal (e.g., computer clock signal) in operation. More particularly, the present invention addresses the problem of clock signaling for computer systems (e.g., servers in datacenters) and more generally for electronic circuit devices which consume clock signal in operation.
Current server, datacenter, and High Performance Computing (or HPC) subsystems are composed of tens to hundreds of densely packed blades, assembled per chassis, rack, and point of delivery (PoD, i.e., a container-sized server cluster). Packaging density and PoD sizes are increasing, whence the key role of packaging and cooling integration.
These systems' operation depends on the existence of a single coherent synchronization source, a.k.a the system clock. For instance, SMP servers require synchronous delivery typically across multiple address busses for snoop-coherency. Other examples include BlueGene's hardware support for synchronization primitives and several other upcoming systems wherein “heart beat” messages are used to detect failures and synchronize operations across multiple boards and racks.
Generating, and especially distributing, a clock over distances larger than a few tens of centimeters is challenging to design from the electromagnetic standpoint, requiring additional electrical power for clock regeneration. Currently, the clock is electrically distributed within a board, chassis, rack, and container through copper wires configured in a complex clock tree topology. This requires finely tuned properties in the desired frequency range, which in turn requires substantial tuning, simulation, and area. Also, inside chips, clock tree architectures are used with frequent power-hungry clock regeneration circuits. In addition, the transition from planar 2D CMOS to 3D stacking chip configurations considerably increases the complexity of signaling, starting with the clock distribution.
More generally, recent evolutions in the IO pin density has led to substantially increased wiring/interconnect densities. The increased density has raised new thermal engineering challenges addressed by fluid instead of air cooling. Recent announcements indicate that at least some of the next generation's large systems will be fluid-cooled, using water, oil, and/or other convenient thermal agents (e.g., by immersion).